1. Field of the Invention
The present invention relates to a non-volatile phase change memory device for rewritably storing data using a change in resistance state of a phase change element, and particularly relates to a phase change memory device in which a memory cell is formed by connecting the phase change element and a diode in series.
2. Description of the Related Art
A non-volatile semiconductor memory device such as a flash memory becomes more important in recent years. Particularly, attention is paid to a phase change memory device as a promising technique, which uses structural change of phase change material. The phase change memory device has a structure in which a resistance state of a phase change element made of the phase change material is changed by heat and thereby data can be rewritably stored. In a write operation of the phase change memory device, joule heat due to current is generated so as to change the resistance state of the phase change element, and thus relatively large write current such as 500 μA to 1 mA is required. Therefore, if a MOS transistor is used as a select switch of the phase change element in a case of configuring a memory cell of the phase change memory device, it needs to have a gate width large enough to flow the write current and a reduction in cell size becomes difficult. On the other hand, a configuration advantageous for reducing the cell size is proposed, in which a diode is used as an select switch for the phase change element (For example, see US 2005/0270883).
FIG. 7 shows a basic configuration of the conventional phase change memory device having memory cells using diodes. In FIG. 7, each of memory cells MC is formed of a phase change element 10 and a diode 11 which are connected in series. The memory cells MC are arranged at intersections of word lines WL and bit lines BL in a matrix form, one ends of phase change elements 10 are connected to the bit lines BL and anodes of diodes 11 are connected to the word lines WL. Since large current can be flown through the diode 11 with a small area, the cell size of each memory cell MC can be reduced so as to reduce an entire area of the phase change memory device.
In the write operation of the phase change memory device shown in FIG. 7, a specified memory cell MC is selected and write current flows along a path P0 from the bit line BL to the word line WL through the memory cell MC. At this point, an operation of writing multi-bit data on the same word line WL at the same time is assumed as well as the write operation of one bit data. In this case, write current for a selected plurality of memory cells MC flows into one word line WL at the same time along a plurality of current paths P0. Since the resistance component of the word line WL is relatively large, the potential of the word line WL rises when large write current flows intensively. As a result, the write current reduces. Further, when reading out the other memory cell MC during the write operation for the specified memory cell MC on the word line WL, an increase in the potential of the word line WL causes noise and high-speed read operation is hindered.
Mean while, a configuration shown in FIG. 8 may be employed in order to avoid current concentration on the word line WL in FIG. 7. In the configuration of FIG. 8, a select transistor 12 is disposed below the same memory cell MC as in FIG. 7. In the select transistor 12, its gate is connected to the word line WL, one end of a diffusion layer D is connected to the anode of each diode 11, and the other end of the diffusion layer D is connected to a ground line GL arranged in parallel with the bit line BL. Thus, a current path P1 for the write operation of the phase change memory device shown in FIG. 8 is formed through the bit line BL, the memory cell MC, the one end of the diffusion layer D of the select transistor 12 and the other end thereof, and reaches the ground line GL. By such a configuration, even when writing the multi-bit data on the same word line WL at the same time, the current concentration on the word line WL is avoided.
However, if the configuration of FIG. 8 is employed, the select transistor 12 connected to a non-selected word line WL remaining at a low level turns off, and thus the diffusion layer D below the non-selected memory cell MC connected to the select transistor 12 becomes a floating state. When reading out the other selected memory cell MC through the same bit line BL as for the above non-selected memory cell MC in such a state, the diffusion layer D in the floating state is charged. Then, the charge current continues to flow until a predetermined time depending on a diffusion layer capacitance elapsed, and in this time period, a state occurs in which the resistance state of the phase change element 10 can not be determined. The select transistor 12 is required to be formed with a large gate width capable of flowing a large write current. Therefore, the diffusion layer capacitance of the diffusion layer D becomes a large value, and the time required for the above charging is correspondingly becomes longer. Particularly, when the phase change element 10 is written to be in the high resistance state, the time required for charging the diffusion layer D becomes further longer so that read speed drastically decreases.